// hardware economics

All signals tagged with this topic

Aug 12

Multi-tier storage becomes essential economics lever for AI inference

Inference workloads now dwarf training in total compute spend, creating pressure to optimize not just raw speed but cost per query. Storage architecture has become the primary control surface. Companies like Anthropic and inference-specialist startups layer fast cache (SRAM/HBM), warm storage (NVMe), and cold storage (HDDs) to reduce the per-token cost of serving large models. The competition is shifting from model capability to operational margins. This favors infrastructure vendors and chip companies selling tiered solutions, while pushing large model providers toward capital-efficient serving rather than bigger parameter counts.

theme-connected semiconductor manufacturing chip production capacity hardware economics

May 11

TSMC delays advanced chip equipment, signaling Moore's Law slowdown

Source: Azeem Azhar, Exponential View

TSMC's decision to shelve ASML's High-NA EUV machines until 2029 exposes a hard economic reality: the cost of maintaining chip density improvements has become prohibitive even for the world's largest foundry. The decades-old assumption that each generation of chips gets smaller, faster, and cheaper is breaking. When the leading edge becomes too expensive to chase, the industry splits between premium players who can afford cutting-edge nodes and a broader market stuck on mature processes. This shifts both competition and investment patterns in semiconductors.